The present invention relates to fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device using a multilayer hard mask layer.
A hole patterning of a micro line width is difficult to accomplish in a process for fabricating a semiconductor device having a line width of 50 nm or less due to a limitation of resolution of present exposure apparatuses. Thus, a double patterning process is used to form a hole which is easier than forming a hole by a hole patterning. The double patterning process is performed by forming lines, wherein each of the lines are crossed.
FIGS. 1A to 1D illustrate perspective views of a method for fabricating a semiconductor device using a typical double patterning process.
Referring to FIG. 1A, an amorphous carbon layer 12 is formed over an etch target layer 11, and a first layer 13 and a second layer are sequentially formed over the amorphous carbon layer 12 as a hard mask.
A first photoresist pattern 15 is formed by performing a first exposure and developing processes. A first patterning is performed to etch the second layer by using the first photoresist pattern 15 as an etch barrier. Reference numeral 14 represents an etched second layer.
Referring to FIG. 1B, after removing the first photoresist pattern 15, a second photoresist pattern 16 is formed by performing a second exposure and developing processes. The second photoresist pattern 16 has a line pattern crossing the first photoresist pattern (represent numeral 15 of FIG. 1A) at right angles.
Referring to FIG. 1C, a second patterning is performed to etch the first layer 13 by using the second photoresist pattern 16 and the etched second layer 14. In accordance with the double patterning process, a first layer pattern 13A has a plurality of openings. Herein, the openings represent patterns such as holes.
The method sequentially performing the first patterning and the second patterning is called as the double patterning process.
After removing the second photoresist pattern 16, the first layer pattern 13A has the plurality of openings, which define contact holes.
Referring to FIG. 1D, the amorphous carbon layer 12 is etched by using the first layer pattern 13A as an etch barrier. Thus, an amorphous carbon layer pattern 12A has a plurality of openings by copying the openings of the first layer pattern 13A.
Although it is not shown, the etch target layer 11 is etched by using the amorphous carbon layer pattern 12A as an etch barrier to form a plurality of patterns. The patterns of the etched etch target layer 11 include contact holes, via holes and storage node holes.
In the above described typical method, the etch process is performed by using the double hard mask having a stacked structure of the first layer 13 and the second layer 14 over the amorphous carbon layer 12.
As described above, when the double patterning process or the double hard mask are used, the limitation of resolution of present exposure apparatuses may be overcome and patterns may have a fine line width at the same time.
However, when the etching process is performed by using the double hard mask having the stacked structure of the first layer 13 and the second layer 14, processing limitations, which will be described hereafter, may occur.
Referring to FIG. 1B, when the first layer 13 is etched, a portion of the first layer 13 is etched by using the second layer 14 as the etch barrier and the rest of the first layer 13 is etched by using the second photoresist pattern 16 as the etch barrier.
Therefore, since the first layer 13 is etched by using different etch barriers, critical dimensions may be undesirably changed.
Furthermore, since the first layer 13 is etched by using different etch barriers at the same etch condition, the etch processes different etch characteristics may occur depending on the different etch barriers. Specially, in case where the first layer 13 is an oxide layer, when the first layer 13 is etched by using the second photoresist layer 16 as the etch barrier, unevenness may occur after performing the etch process. Herein, the unevenness causes a winding pattern. This is because etch tolerance of the second photoresist pattern 16 is insufficient due to characteristics of the oxide layer etcher having a high ion energy. That is, when the etch process is performed using the oxide layer etcher, the second photoresist pattern 16 is transformed because of ion bombardment of the ion having the high ion energy.
FIG. 2 is a photograph showing the unevenness of the second photoresist pattern in accordance with a typical method. It is seen that the unevenness of the second photoresist pattern, reference numeral “W” of FIG. 2, occurs.